1. Field of the Invention
The present invention relates to a transmission apparatus which is connected between various data processing equipment such as a personal computer, an office computer, a word processor, and a printer to transmit data and, more particularly, to an optical transmission apparatus for optically transmitting data between the equipment.
2. Description of the Related Art
A so-called multi-core cable or a flat cable has been conventionally used as a cable which connects a computer and a printer. Since these cables include a bundle of wires, electromagnetic waves generated from the wire cables are picked up and amplified by surrounding radio and electronic equipment as noise, thus adversely affecting this equipment. Therefore, an optical transmission apparatus for connecting an optical fiber cable between data equipment, and for transmitting data as serial data has been proposed (Published Unexamined Japanese Patent Application No. 60-141051).
In a conventional optical transmission apparatus, optical transmission/reception modules each having the same number of pins and the same pin arrangement as those in a receptacle are respectively arranged on a printed circuit board incorporated in a CPU of a personal computer and a printed circuit board incorporated in a printer to allow replacement with a conventional receptacle. These optical transmission/reception modules are optically coupled to each other through an optical fiber cable having a two-core structure. Each optical transmission/reception module is connected to the optical fiber cable through an optical connector.
In each optical transmission/reception module, input data to be transmitted, a data write signal (WD signal), and a control signal are input to an input buffer as parallel input signals. Thereafter, these signals are held by a data hold circuit. The data hold circuit holds the parallel input signals during a sampling period T during which a next stage parallel/serial conversion circuit samples data, and assures that the parallel input signal is reliably sampled at a sampling timing Sm. The parallel/serial conversion circuit converts the parallel input signal into a serial signal, and the converted serial signal is properly modulated by a transmission circuit. The modulated signal is converted into an optical signal by a light-emitting diode and the optical signal is transmitted.
The transmitted optical signal is transmitted through an optical fiber cable, and is converted into an electrical signal by a photodiode. This electrical signal is properly demodulated by a receiving circuit. Thereafter, the demodulated signal is converted into a parallel signal by the parallel/serial conversion circuit, and the converted signal is output through an output buffer.
Parallel data output from the CPU includes a data write signal (WD signal) for controlling write timing of the data. This WD signal is converted into serial data together with the parallel data, and the converted serial data is transmitted. Normally, this WD signal is a pulse having a small width which is generated during an output period of the parallel data, and is entirely included in the parallel data. All the pulse widths of the parallel outputs from the serial/parallel conversion circuit are equal to each other. For this reason, this conventional apparatus includes a first delay circuit for delaying the leading edge of the WD signal included in output signals from the output buffer by .tau. 1, and a second delay circuit for delaying the trailing edge of the output data by .tau. 2. The WD signal is perfectly included in the output data by these two delay circuits.
In the above-mentioned conventional optical transmission apparatus, a sampling time of a parallel input signal is fixed on the optical transmission apparatus side. Therefore, an input period of the parallel input signal cannot be shorter than the sampling period. This is an obstacle which occurs when the above optical transmission apparatus is applied to various equipment having different data processing or transmission speeds.
The data hold circuit holds the parallel input data during a sampling period T from the trailing edge of the data This period is set to achieve reliable sampling of, e.g , a WD signal having a relatively small pulse width. Single input data having a large pulse width is, however, sampled more than two times, i.e., multiple-sampled. For this reason, a countermeasure against this multiple sampling has been required.